A study of different encoding techniques applied on high-capacitance buses for low-power processor design
In this thesis, the effectiveness of applying 10 different bus-encoding techniques to lower the power consumption of processors is investigated. A standard cell based design methodology was followed in the implementation of the encoder and decoder circuits. The bus lines targeted are the instruction...
| Prif Awdur: | |
|---|---|
| Fformat: | Traethawd Ymchwil |
| Iaith: | Saesneg |
| Cyhoeddwyd: |
2004.
|
| Pynciau: |