A study of different encoding techniques applied on high-capacitance buses for low-power processor design
In this thesis, the effectiveness of applying 10 different bus-encoding techniques to lower the power consumption of processors is investigated. A standard cell based design methodology was followed in the implementation of the encoder and decoder circuits. The bus lines targeted are the instruction...
| मुख्य लेखक: | |
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| स्वरूप: | थीसिस |
| भाषा: | English |
| प्रकाशित: |
2004.
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| विषय: |