A study of floating-point architectures for pipelined RISC processors - Reyes, Joy Alinda P. (2005)
As embedded applications become more complex, the demand for computing power increases. To achieve this needed increase in the computing performance of embedded microprocessors, improved implementations of floating-point units (FPUs)are used. However, no structured methodology is available in designing FPUs and thus, there is a need to analyze the suitability of floating-point architectures for high speed or low power applications. In this thesis, different system-level architectures and operational algorithms of FPU, were implemented using 0.25um CMOS standard cells and analyzed. Fair comparison of design metrics in terms of speed, area and power consumption were made and analyzed for each design. Results show that architectures with an independent pipeline for division perform better in terms of speed while combined pipelines consume the least power. Architectures with a combined pipeline for addition and multiplication and an independent pipeline for division occupy the smallest layout area and, in general, show the best performance in all three metrics.
Thesis (M.S. Electrical Engineering)--University of the Philippines, Diliman.
Keywords: Computer architecture; Floating-point arithmetic; Computers, Pipeline; RISC microprocessors