High-level implementation of the ARM7 microprocessor - Delarmente, Jonathan T. (2004)
The ARM 7 belongs to the Advanced RISC Machines (ARM) family of general-purpose 32-bit microprocessors, which offer very low power consumptions for high performance devices. The architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set is much simpler in comparison with micro-programmed Complex Instruction Set Computers (CISC). The use of pipelining allows for the continuous operation of all parts of the processing and memory systems. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. This implementation results in performance speedup by increasing the throughput of the microprocessor. The implementation employed two levels, namely Behavioral Level and Register Transfer Level (RTL). The behavioral model was designed using Very High Speed IC Hardware Description Language (VHDL). The model was synthesized using standard cells on a 0.25 um CMOS process. This, together with analysis and simulation, was performed using Cadence Design Systems. After validation of correct functionality, it was modeled at the RTL. Performance was evaluated according to several significant parameters such as throughput, hardware complexity, and maximum usable clock frequency. The observed maximum power was 6.115 mW while the observed minimum power was 2.197 mW. The maximum usable clock frequency is 10 MHz while the measured area was 1.78 mm by 1.17 mm.