All digital phase-locked loop frequency synthesizer - Cruz, James Ronald B. (1997)
The project objective is to design a phase-locked loop frequency synthesizer using only digital components. The pll is tasked to ensure that the frequency generated is stable. Various phase-locked loop design blocks has been tested to know which could be best adapted to the ADPLL system. Because of the orientation of these circuits with analog components reconfiguration has been performed to ensure the optimum performance of the digital design. Control of the PLL system could be done manually using a keypad with display or Universal Serial Bus (USB) interface. The digital design has been implemented in Xilinx Field Programmable Gate Arrays (FPGA) using Visual HDL synthesis. Twenty programmable frequencies can produced by the circuit.
Thesis (B.S. E.E.)--University of the Philippines Diliman.
Keywords: Frequency synthesizers -- Design and construction; Phase-locked loops; Digital electronics; Phase-locked loop frequency synthesizer