Implementation of a dynamically reconfigurable encoder-decoder multiplier system using FPGAs - Antonio, Ginia G. (1999)
This project is a proof of concept that demonstrates the advantages of in-system reconfiguration and the flexibility of the Field Programmable Gate Array as a reconfigurable unit. Field Programmable Gate Arrays or FPGA's are devices that feature a gate-array like architecture with a matrix of configurable logic blocks surrounded by a periphery of I/0 blocks. Segments of metal interconnects can be linked in an arbitrary manner by programmable switches to form the signal nets between these blocks. FPGAs combine an abundance of logic gates, registers and I/Os with fast system speed and have been used for implementing different designs for digital logic. System designers have extended the flexibility of FPGAs and employed them in reconfigurable computing devices. Reconfigurable computers allow us the ability to modify a computer systems hardware architecture in real time and are advantageous in systems where the design of the hardware may change in response to the demands placed upon the system while it is running. The objective of this project is to design a system that automatically reconfigures itself during run-time according to the hardware application in demand. The hardware applications involved are an encoder and a decoder using the Hamming code, an 8 by 8 multiplier using Booth's Algorithm, and the control circuit that processes information and generates signals that will reconfigure the FPGA during run time. The system's implementation is composed of coding, simulating and synthesizing each hardware application design using Cadence/Leapfrog Software tools, and downloading these designs on a Xilinx 4003e FPGA. The final product is a functional board that proves the feasibility of a dynamically reconfigurable encoder-decoder-multiplier system.