Implementation of a dynamically reconfigurable encoder-decoder multiplier system using FPGAs

This project is a proof of concept that demonstrates the advantages of in-system reconfiguration and the flexibility of the Field Programmable Gate Array as a reconfigurable unit. Field Programmable Gate Arrays or FPGA's are devices that feature a gate-array like architecture with a matrix of c...

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Bibliografske podrobnosti

Glavni avtor:	Antonio, Ginia G.
Drugi avtorji:	Raquepo, Lucita P.
Format:	Thesis
Jezik:	English
Izdano:	1999.
Teme:	Field programmable gate arrays. Error-correcting codes (Information theory) Encoder-decoder-multiplier system. Hamming code. Multiplier system.