Antonio, G. G., & Raquepo, L. P. (1999). Implementation of a dynamically reconfigurable encoder-decoder multiplier system using FPGAs.
Chicagoスタイル(17版)引用形式Antonio, Ginia G., , Lucita P. Raquepo. Implementation of a Dynamically Reconfigurable Encoder-decoder Multiplier System Using FPGAs. 1999.
MLA(9版)引用形式Antonio, Ginia G., , Lucita P. Raquepo. Implementation of a Dynamically Reconfigurable Encoder-decoder Multiplier System Using FPGAs. 1999.
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