Implementation and optimization of the ARM7 microprocessor with single-level cache - Agabao, Joscel Ann Reyes (2005)
The ARM7 microprocessor is a Reduced Instruction Set Computer (RISC) which is used in application-specific integrated circuits. Its simple load-store architecture and 32-bit instruction size is ideal for low-power and low cost embedded applications. The ARM7's small die size makes it suitable for integrating it into a larger custom chip that could also contain other cells. ARM7 employs pipelining to improve the utilization of the hardware resources and to gain significant speedup. Typically, while one instruction is being executed, the next one is being decoded, and the third is being fetched from the memory. The main objective of the project is to provide an optimized implementation of the ARM7 microprocessor with a single level cache using Very High-Speed Integrated Circuit Hardware Description Language (VHDL). The implementation employed four levels of abstraction, namely behavioral level, register transfer level, gate level, and place and route for the ARM7. Behavioral and RTL levels were employed for the integrated ARM7 and Level 1 Cache. The model was synthesized using standard cells on a 0.25um CMOS process. Simulation, synthesis, and place and route were done using the Cadence Design Systems Software. Performance was evaluated according to several significant parameters such as throughput, hardware complexity, speed and area. Comparison with the previous ARM7 implementation was also recorded. The measured area of the optimized ARM7 was 1.105 mm2 with a working frequency of 25 MHz. The measured minimum and maximum power are 1.11212 mW and 1.69793 mW respectively. Insertion of cache significantly improved the processor performance. ARM7 with cache completed an instruction mix in 826 clock cycles as compared with 6622 clock cycles as compared with 6622 clock cycles if a memory with 10 cycle delays is to be used. The result is also comparable to 661 clock cycles if an ideal memory with a single cycle per access.