Design and implementation of ARM7 microprocessor with single-precision floating-point coprocessor - Abatayo, Jose Francisco T.; Densing, Chris Vincent J.; Magnaye, Christian O. (2007)
Applications that contain complex computer algorithms and programs often consist of floating-point (FP) operations. Several researches in the Intel Microprocessors Laboratory have dealt with different ARM7 implementations, but none of these include a floating-point unit (FPU). The project's goal was to implement an ARM7 Microprocessor with an FP coprocessor that could handle single-precision FP operations. The FPU was implemented using a class 2 FPU architecture, which used a combined unit for addition and multiplication, and an independent unit for division. The project was implemented using VHDL, which is a high-level hardware description language. Functionality was verified using the Cadencen Design System Software. The design's schematic and layout was generated using Cadencen, and was implemented in standard cells for a 0.25um CMOS process. Aside from functionality, the final implemented design was characterized in several metrics such as speed, area, and power consumption. Performance was measured using three different metrics namely power, area and maximum allowable frequency. The average power measured was 40.32 mW. The chip area was 2.525 square millimeters and the maximum allowable frequency was 10 MHz.
Thesis (B.S. CoE)--University of the Philippines Diliman.
Keywords: Microprocessors -- Design and construction; Floating-point arithmetic; Floating point operations; ARM7 microprocessor