FPGA implementation of space-time encoders - Fadera, Geoffrey Nicolas D.; Ignacio, Lyand Richwell T. [BS ECE].; Nastor, Mark Benson R. [BS CoE].; Urriza, Paulo Isagani M. [BS CoE]. (2007)
Performance of high data-rate, wireless communication systems depends heavily on coding. To maintain a reliable system, transmit and receive diversity techniques have been suggested. One of these techniques is Space-Time Coding. It has gained interest for the research community over the last decade, which led to the discovery of different space-time codes. However, performance evaluations of most of these codes have only been done through simulations. To realize the hardware performance of space-time codes, this project implemented four ST encoders with four transmit antennas namely, space-time block code (STBC), space-time trellis codes (STTC), space-time block coded OFDM (STBC-OFDM), and space-time trellis coded OFDM (STTC-OFDM), in a Field Programmable Gate Array (FPGA). The Altera Stratix DSP Development Kit containing the EP1S25 FPGA chip was used. Channel simulation and Space-Time Decoding were done in Matlab. Performance of the different schemes were investigated individually, and then compared in terms of bit-error rate, FPGA utilization, and achievable bit rate.
Thesis (B.S. Computer Engineering and B.S. Electronics and Communications Engineering)--University of the Philippines, Diliman.
Keywords: Field programmable gate arrays; Space time codes; Trellis decoder; Space time encoders; Space-Time Trellis Codes (STTC).; Space-time Block Codes (STBC).