Development of a 32-bit floating point 3 dimensional vector microprocessor
The aim of the project is to develop a three dimensional vector microprocessor modelled in VHDL (Very High Speed Integrated Circuit Hardware Description Language). It is patterned after scalar processor-based design architectures implemented in multiple cycles but it is not pipelined. It can perform...
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| Natura: | Tesi |
| Lingua: | English |
| Pubblicazione: |
1997.
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