Development of a 32-bit floating point 3 dimensional vector microprocessor
The aim of the project is to develop a three dimensional vector microprocessor modelled in VHDL (Very High Speed Integrated Circuit Hardware Description Language). It is patterned after scalar processor-based design architectures implemented in multiple cycles but it is not pipelined. It can perform...
| Auteur principal: | |
|---|---|
| Format: | Thèse |
| Langue: | English |
| Publié: |
1997.
|
| Sujets: |