A study of the effects of layout techniques on the noise performance of CMOS RF transistors - Pornela, Crimson Salas (2003)
This thesis aims to study and analyze the effects of different layout strategies on the noise performance of CMOS RF transistors. Layout of NMOS transistors were designed and implented in common-source and cascode configurations using TSMC's 0.25 um CMOS process. Two general layout approaches were used: the multifinger distribution and cluster of fingers arrangement. The gate geometry of the transistors is varied using single-contacted and double-contacted gate. Substrate contacts are implemented either in guard rings or conventional substrate contacts. For matching purposes, dummy transistors and dummy polysilicon were utilized. The implemented transistors are placed inside a test fixture with ground-signal-ground (GSG) probe pads. Simulations were accomplished using Cadence SpectreRF, wherein the noise figure and noise parameters can be obtained. Three simulation strategies were used to extend the BSIM3v3 model for RF noise simulation: (1) simulation with calculated Rg, (2) simulation with extracted components (Rg, Rsub, Cdb) and (3) simulation that takes into account the effect of the test fixture and addition of extracted components. The fabricated transistors were characterized and measured using a micromanipulator with GSG probes, a network analyzer and a noise figure measurement system. From the simulated and measured data, the layout strategies that affect the noise performance of the transistors were determined and analyzed.