A study of the effects of layout techniques on the noise performance of CMOS RF transistors

A study of the effects of layout techniques on the noise performance of CMOS RF transistors

This thesis aims to study and analyze the effects of different layout strategies on the noise performance of CMOS RF transistors. Layout of NMOS transistors were designed and implented in common-source and cascode configurations using TSMC's 0.25 um CMOS process. Two general layout approaches w...

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Bibliographic Details
Main Author: Pornela, Crimson Salas
Format: Thesis
Language:English
Published: 2003.
Subjects:
Metal oxide semiconductors, Complementary > Design and construction.
Transistors > Noise > Simulation methods.
Radio frequency integrated circuits > Design and construction.