A study on using dual supply voltages for low power design of datapath elements for a RISC microprocessor - Te, Archie Co (2003)
Power consumption has increasingly become a major focus in digital systems design. As the demand for portable applications increases, many low power design techniques have been proposed. Most of these techniques target the dynamic component of power consumption, or power consumed during switching. Voltage scaling, which involves reducing the supply voltage, is an effective technique to reduce dynamic power consumption since it takes advantage of the quadratic dependence of power on voltage. However, reducing supply voltage results in increased propagation delay. A possible approach in voltage scaling is to use dual supply voltages to allow parts off the critical path of the logic network to operate at a lower supply voltage while maintaining the same effective speed. In this thesis, some dual supply voltage techniques are applied to basic adder topologies. Comparisons are made regarding their effectiveness and applicability to datapath elements. A faster procedure is proposed for the selection of low voltage gates. Another procedure is suggested to quantify the cost of level converters. The power saving potential of dual supply voltage adders and datapath elements is analyzed based on simulations. Physical layout tradeoffs are considered.