A study of selective power-down optimization techniques for low-power integrated RISC execution unit design - Bantug, Arianne Contemprato (2003)
In this thesis, selective power-down techniques are used for system level optimization. Using these techniques, parts of the system that are idle in every clock cycle are disabled, thus reducing dynamic switching power. This concept is implemented by clock gating, control-signal gating and disabling output bus drivers. These three techniques were used separately in the execution unit of a DLX-based microprocessor. A quantitative analysis of power savings and trade offs were made based on simulations of their schematic implementations. A new optimization procedure that uses all three techniques to maximize dynamic switching power reduction is also proposed and implemented resulting in up to 37% power savings. The resulting power savings and area overhead of the optimized designs obtained from both schematic and layout implementations were analyzed and compared.