A study of selective power-down optimization techniques for low-power integrated RISC execution unit design
In this thesis, selective power-down techniques are used for system level optimization. Using these techniques, parts of the system that are idle in every clock cycle are disabled, thus reducing dynamic switching power. This concept is implemented by clock gating, control-signal gating and disabling...
| Päätekijä: | |
|---|---|
| Aineistotyyppi: | Opinnäyte |
| Kieli: | English |
| Julkaistu: |
2003.
|
| Aiheet: |