A study of the effects of pipeline modification techniques on the performance and power consumption of the DLX microprocessor - Borja, Richard B. (2004)
In this thesis, two Stake-skip pipeline-level power optimization techniques namely: (1) the Stage-skip IF and (2) the Stage-skip MEM techniques are studied. These techniques bypass stages that are not needed in the execution of certain instructions, thus effectively reducing the power consumption of the processor. The effects of each technique on the power consumption and silicon area, when applied to a 32-bit 5-stage pipelined DLX microprocessor, are analyzed and quantified. The power savings and corresponding area trade-offs are also evaluated with respect to this base microprocessor. Different test benchmarks are used to compute for the processors power. Power savings of up to 65% with an overhead area of up to 20% are realized for Stage-skip IF techniques, and power savings of up to 65% with an area overhead of 3% are achieved for Stage-skip MEM technique.
"June 2004."
Thesis (M.S. Electrical Engineering : Microelectronics option)--University of the Philippines, Diliman.
Keywords: Computer engineering; Computers, Pipeline