A study of selective power-down techniques for low-power RISC microprocessor design - Khalid, Sihawi Abdulhamid (2004)
In this thesis, selective power-down techniques for low-power RISC microprocessor design sre studied. Selective-power down techniques are register transfer level power optimization techniques that target dynamic switching power. These techniques effectively reduce power consumption by selectively shutting down parts of a system that are not doing useful work. The selective power-down techniques considered in this thesis are (1) clock gating, (2) control-signal gating, (3) precomputation. Each technique is applied separately to the DLX microprocessor are quantified. Optimization approaches that combine different selective power-down techniques to maximize power savings are then proposed and implemented. Resulting power savings and area tradeoffs of all implementations are analyzed and compared. The results of this study serve as a basis for evaluating the different selective-power down techniques in terms of the effect of each technique on the power consumption and area of a RISC microprocessor. This study shows that clock gating achieves the highest power savings. Clock gating techniques reduces total DLX power by 50% and also reduces chip area by 3%.
"May 2004."
Thesis (M.S. Electrical Engineering)--University of the Philippines Diliman.
Keywords: RISC microprocessors -- Statistical power analysis; RISC microprocessors -- Switching power supplies; Clock gating; Control signal gating; Precomputation