An asynchronous single-precision floating-point arithmetic unit - Noche, Joel Reyes
A transistor-level design of an asynchronous single-precision floating-point arithmetic unit is designed and tested using Cadence software. It uses CMOS (complementary metal oxide semiconductor) and DCVS (differential cascode voltage switch) logic in a 0.35 um process. Dual-rail signals are used for data, and control signals use four-phase handshaking and are mostly single-rail. Layouts of some of the unit's datapath and control blocks are created and tested. The unit handles single-precision addition, multiplication, division, and remainder using the IEEE 754-1985 Standard for Binary Floating-Point Arithmetic, with rounding and other operations to be handled by separate hardware or software. Division and remainder are done using a restoring subtractive algorithm; multiplication uses an additive algorithm. Exceptions are noted by flags (and not trap handlers) and the output is in single-precision. Previous work on asynchronous floating-point arithmetic units have mostly focused on single operations such as division. This work performs four floating-point operations using a common datapath. As such, it can serve as a basis of comparison for future work.