An asynchronous single-precision floating-point arithmetic unit
A transistor-level design of an asynchronous single-precision floating-point arithmetic unit is designed and tested using Cadence software. It uses CMOS (complementary metal oxide semiconductor) and DCVS (differential cascode voltage switch) logic in a 0.35 um process. Dual-rail signals are used for...
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| フォーマット: | 学位論文 |
| 言語: | English |
| 出版事項: |
2003.
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