A study of the effects of layout on RF MOSFET small-signal parameters - Gutierrez, Maria Cecilia Nera (2003)
The goal of this thesis is to study and to analyze the effects of layout on RF MOSFET small-signal parameters. Using TSMC's 0.25 um CMOS process, 50 test structures, which include 46 RF MOSFET's and 4 de-embedding standards, were implemented and fabricated. RF MOSFET's representative of various layout techniques, were implemented in both common source and cascode configurations. All RF MOSFET's were placed inside a test fixture with GSG probe pads. The other four structures (open, short1, short2, and thru) are standards required by open and three-step de-embedding. A Micromanipulator (with microwave coplanar GSG probes) and a network analyzer were used in measuring the S-parameters of the fabricated RF MOSFET's. The bias voltages were provided by a parameter analyzer, along with a bias tee. Results of pad parasitics de-embedding and RF MOSFET parameter extraction were presented. The effects of gate geometry, number of fingers, placement of substance contacts, routing scheme, and dummy structure on the extracted parameters were collated and analyzed. Finally, the effects of cascode width on the transistor gain and its reverse isolation were presented.
Thesis (M.S. Electrical Engineering)--University of the Philippines, Diliman.
Keywords: Metal oxide semiconductors field-effect transistors -- Mathematical models; Radio frequency