A matrix representation for the verification of well-handledness of the Robustness Diagram with loop and time controls
Well-handledness in Robustness Diagrams with Loop and Time Controls (RDLT) is important, as it ensures proper termination and liveness for all workflows. Moreover, verifying well-handledness in Robustness Diagrams with Loop and Time Controls provides a structural method to verify classical soundness...
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| フォーマット: | 学位論文 |
| 言語: | English |
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