Automation of verification of well-handledness in Robustness Diagram with Loop and Time Controls - Nique, Kim C.; Malinao, Jasmine A. (Tacloban City Division of Natural Sciences and Mathematics, University of the Philippines Tacloban College, 2025)
This study addresses the absence of an automated tool for verifying the well-handledness of Robustness Diagrams with Loops and Time Controls (RDLTs). It introduces an automation module integrated into the existing verification tool for RDLTs, enhancing its ability to assess well-handledness properties. Grounded in established literature, this work adopts the formal definition of well-handledness for RDLTs and extends se-lected algorithms and code implementations for verifying loop-safeness of components including Noncritical Arcs (NCAs) and safeness of Critical Arcs (CAs). To support tool integration, a dedicated parser is developed to process RDLT inputs and con-struct internal data structures representing RDLT components. The Edmonds-Karp algorithm is employed to identify disjoint paths critical to the verification process, Additionally, an algorithm for targeted activity extraction is implemented to identify activities associated with well-handledness violations. The tool also generates a com-prehensive report detailing the nature of the violations and the specific components involved.
Undergraduate thesis (Bachelor of Science in Computer Science) -- University of the Philippines, Tacloban.
Includes bibliographical references.
Keywords: Software engineering