Finite state machines in hardware theory and design (with VHDL and SystemVerilog)

Finite state machines in hardware theory and design (with VHDL and SystemVerilog)

すべてのバージョン（2件）を表示する
書誌詳細
第一著者: Pedroni, Volnei A. (著者)
フォーマット: Electronic Resource
言語:English
出版事項: Cambridge, Massachusetts The MIT Press [2013]
主題:
Electronic books.
SystemVerilog (Computer hardware description language)
VHDL (Computer hardware description language)
Sequential machine theory > Data processing.
Computer systems > Mathematical models.
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