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  1. 1

    Latchup-free ESD protection design with complementary substrate-triggered SCR devices. per Ming-Dou Ker

    Article

    Latchup-free ESD protection design with complementary substrate-triggered SCR devices.
  2. 2

    Substrate-triggered SCR device for on-chip ESD protection in fully silicided sub-0.25-μm CMOS process. per Ming-Dou Ker

    Article

    Substrate-triggered SCR device for on-chip ESD protection in fully silicided sub-0.25-μm CMOS process.
  3. 3

    Design on ESD protection scheme for IC with power-down-mode operation. per Ming-Dou Ker

    Article

    Design on ESD protection scheme for IC with power-down-mode operation.

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